1. Field of the Invention
This invention relates to configurable input/output ports used in peripheral devices, and in particular to input/output ports configured with both volatile and non-volatile configuration circuitry.
2. Description of the Related Art
In a typical application of a microcontroller or microprocessor, the microcontroller or microprocessor interfaces with several peripheral devices to accomplish various tasks. Typically, a custom circuit board must be designed to provide the microcontroller or microprocessor with needed interfaces and external services. The number and combination of peripheral devices needed on the circuit board depend on the application.
A Programmable System.TM. Device ("PSD") manufactured by Wafer Scale Integration, Inc. provides a compact, convenient, and flexible way to provide both interfaces and services in an application of a microcontroller or microprocessor. PSDs are integrated circuits which provide on one die a multiplicity of distinct functional units. For example a PSD may contain a ROM unit, a RAM unit, a programmable array logic (PAL) unit and configurable logic blocks.
Configurable peripheral ports on a PSD connect functional units of the PSD to external devices including, for example, external memory, external logic circuits, microcontrollers, and microprocessors. Using configurable ports and functional units, a PSD can replace many different combinations of peripheral devices. In a particular application, a single PSD chip can provide memory and logic, can serve as "glue" between devices in an application, and can create interfaces between devices operating under different protocols. With nonconfigurable devices, many separate ICs are required to provide the same functions.
Configurable peripheral ports generally include I/O pins, circuitry for routing input or output signals to or from the I/O pins, and configuration circuitry to control the routing. FIG. 1 illustrates an I/O pin 100 from a configurable peripheral port. Typically, several I/O pins, such as I/O pin 100 are grouped together to form a port. An input select multiplexer 103 and an output select multiplexer 102 route, in accordance with control signals on bus 105A, the signals that pass through I/O pin 100. As shown in FIG. 1, some typical signals to be routed through output select multiplexer 102, buffer 101 and output from I/O pin 100 include a "Latched address" signal, a "Register-out" signal, and an "Alternate function out" signal. Input signals are routed through I/O pin 100, lead 104, and input select multiplexer 103. Typical input signals include "Alternate Function In," "Status In," and "Address Input". Input select multiplexer 103 routes each input signal to the proper one of lines 103A, 103B, and 103C in accordance with control signals on bus 105A.
Configuration of I/O pin 100 depends on volatile configuration circuitry 106. Volatile configuration circuitry 106 can be, for example, flip-flops, registers, or one or more memory cells from an SRAM or a DRAM. Volatile configuration circuitry 106 retains configuration data (also referred to as configuration bits) while power is applied but loses data when power is off. At start-up, when power is initially applied, I/O pin 100 is typically unusable because configuration data is not correctly set.
After start-up, a microcontroller (not shown) writes configuration data to volatile configuration circuitry 106 using data line 106A, address line 106B, and write line 106C. Volatile configuration circuitry 106 controls, via bus 105A, the signals which pass through multiplexers 102 and 103.
Volatile configuration circuitry 106 also controls the state of buffer 101. In one state, buffer 101 passes output signals from multiplexer 102 to I/O pin 100. In another state, buffer 101 blocks output signals from multiplexer 102, thereby allowing input signals to be driven from I/O pin 100 to input multiplexer 103 via line 104.
Volatile configuration of configurable ports has the advantage of flexibility. A microcontroller changes the configuration of an I/O port simply by writing new configuration data, and a single I/O pin can be switched among several different uses. Using volatile circuitry for configuration also has major disadvantages:
1) the volatile configuration circuitry must be initialized with configuration data before an I/O pin can be used, therefore volatile configuration cannot be used for access that must be usable at start-up; and
2) software errors can write incorrect configuration data to volatile circuitry and disable an I/O pin.
Another type of configuration used in some configurable ports is pin based configuration. With pin based configuration, an external voltage applied to a configuration pin on an IC controls the configuration of one of the IC's I/O ports. For example, a low voltage applied to a configuration pin on some microcontrollers configures an I/O port as a data port, while a high voltage on the configuration pin permits other uses of the I/O port.
Pin based configuration can be practical in simple I/O ports where a single configuration pin configures an entire port. But in many configurable ports, each I/O pin must be individually configurable and requires several configuration bits. If each configuration bit is provided by a separate configuration pin, the number of configuration pins required for complex configurable port is excessive. Accordingly, pin based configuration is impractical for many applications.
Many prior art devices, such as PLDs, use non-volatile circuitry to control the configuration of I/O ports. U.S. Pat. No. 4,124,899 issued Nov. 7, 1978 to Birkener et al., incorporated herein by reference in its entirety, provides details regarding the operation of PLDs. FIG. 2 shows a prior art PLD macrocell 250 with I/O pin 200. A PLD (or a PAL unit in a configurable peripheral) generally contains several PLD macrocells like PLD macrocell 250. By blowing fuses or anti-fuses in a programmable array (not shown) and setting non-volatile configuration circuitry 207A and 207B, a user programs PLD macrocell 250 to perform a desired logic or arithmetic function. Non-volatile configuration circuitry is typically implemented using fuses, antifuses, or one or more cells from ROM, PROM, EPROM, FLASH, or E.sup.2 PROM.
Signals to be processed by PLD macrocell 250 are fed into the programmable array (not shown) via lines such as 220A and 220B. Signals from the programmable array are routed to a set of AND gates 214, and output signals from the set of AND gates 214 are sent to input leads of an OR gate 210. In general, PLD macrocell 250 could have a programmable array between AND gates 214 and OR gate 210.
An output signal from OR gate 210 is sent to an input lead 213D of flip-flop 213. Flip-flop 213 provides an output signal and an inverted output signal that are registered with a clock signal on lead 213C. The registered output signals are provided on input leads of a multiplexer 212. The output signal from OR gate 210 is also provided to multiplexer 212 directly or inverted through inverter 214. Non-volatile configuration circuitry 207A and 207B select the output signal of multiplexer 212.
A signal on line 205, a product-term signal from the programmable array (not shown), enables or disables inverter 201, typically disabling inverter 201 when I/O pin 200 is used for input. Multiplexer 217 selects the signal which will be fed back to the programmable array through buffer/inverter 218.
Non-volatile configuration circuitry retains configuration data after power-down and provides correct configuration at start-up. Accordingly, non-volatile configuration has the advantage of permitting an I/O port to be used without being initialized by a microprocessor. Correct configuration at start-up is necessary for many I/O functions, such as data buses and PLDs. Another advantage of non-volatile configuration is that configuration can be made immune to software errors which incorrectly change the configuration.
Non-volatile configuration also has disadvantages. Prior art ports with non-volatile configured circuitry are typically dedicated to specific uses and cannot be used with any other functions. Such ports lack flexibility, and are wasted when an application of the peripheral device does not need the dedicated functions. Such ports do not permit a microprocessor to reconfigure the port as needed.
Another problem with prior art configurable I/O ports is the amount of configuration circuitry required. In a complicated I/O port, each I/O pin requires configuration circuitry to provide several configuration bits. The configuration circuitry increases the size and cost of an integrated circuit.
A new type of configurable port is needed which can be configured to connect any of a number of different external devices to any of the different functional units provided on the configurable peripheral device. The ports should provide the flexibility of volatile configuration which is software programmable and should be able to access functional units required at start-up. The ports should efficiently use configuration circuitry to decrease the wafer area needed for fabrication. Greater flexibility would permit more functional units to be addressed with fewer I/O pins, permit tailoring of an integrated circuit to address the needs of customer specific applications, and provide more usable functions at lower cost.